電子發(fā)燒友App
`timescale 1ns/1ns
module IO_KZ(Data,P27,WR,RD,ALE,CLR,OUTKEY,OUT30,CS,CS1,LEDCS,OC);
inout [7:0]Data;
input WR;
input P27;
input RD;
input ALE;
input CLR;
input OC;
input [4:0]OUTKEY;
output [59:0]OUT30;
output [1:0]CS;
output CS1;
output [14:0]LEDCS;
reg?? [14:0]LEDCS;
reg?? [59:0]OUT30;
reg?? [1:0]CS;
wire?? CS1;
//wire [7:0]Data;
reg?? [8:0]IOADD;
reg?? [15:0]DataBF;
reg?? wr_en;
reg?? [7:0]OUTKEYBF;
//wire?? [7:0]OUTKEYBF1;
assign CS1=((IOADD==338)&&(OC==0))?1'b0:1'b1;//8052
assign Data=((IOADD==277)&&(OC==0)&&(RD==0))?OUTKEYBF:8'bzzzzzzz;//8015
always @(OUTKEY)?????
????? begin
????? if(OUTKEY[0]==0)
????? OUTKEYBF<=1;???
????? else if(OUTKEY[1]==0)
????? OUTKEYBF<=2;
????? else if(OUTKEY[2]==0)
????? OUTKEYBF<=3;
????? else if(OUTKEY[3]==0)
????? OUTKEYBF<=4;
????? else if(OUTKEY[4]==0)
????? OUTKEYBF<=5;
????? else
????? OUTKEYBF<=0;
????? end
always @(negedge ALE)
????? begin
????? IOADD<={P27,Data};//ALE下降延讀地址
????? end
always @(IOADD or WR) //WR下降延寫數(shù)據(jù)
????? begin
????? if((IOADD>256)&&(IOADD<337)&&(IOADD!=277))wr_en<=WR;
????? else
????? begin
????? wr_en<=1;
????? end
????? end
always @(negedge wr_en or posedge OC or posedge WR) //WR下降延寫數(shù)據(jù)
??? begin
??? if(OC)
????? begin
??????????????? CS=2'b00;?????????????????????????????
? LEDCS=15'b00000_0000_0000_00;
????? end
??? else if(WR)
??????????????? begin
??????????????? CS=2'b00;???????????????????????????????
????? end???
??? else
??????????????? begin
??????????????? case(IOADD)
??????????????? 261: begin CS=2'b01; end//8005???????????????
??????????????? 262: begin CS=2'b10;LEDCS=15'b00000_0000_0000_01;end//8006
??????????????? 263: begin CS=2'b10;LEDCS=15'b00000_0000_0000_10;end//8007
??????????? 264: begin CS=2'b10;LEDCS=15'b00000_0000_0001_00;end//8008
??????????? 265: begin CS=2'b10;LEDCS=15'b00000_0000_0010_00;end//8009
??????????? 266: begin CS=2'b10;LEDCS=15'b00000_0000_0100_00;end//800A
??????????? 267: begin CS=2'b10;LEDCS=15'b00000_0000_1000_00;end//800B
??????????? 268: begin CS=2'b10;LEDCS=15'b00000_0001_0000_00;end//800C
??????????? 269: begin CS=2'b10;LEDCS=15'b00000_0010_0000_00;end//800D
??????????? 270: begin CS=2'b10;LEDCS=15'b00000_0100_0000_00;end//800E
??????????? 271: begin CS=2'b10;LEDCS=15'b00000_1000_0000_00;end//800F
??????????? 272: begin CS=2'b10;LEDCS=15'b00001_0000_0000_00;end//8010
??????????? 273: begin CS=2'b10;LEDCS=15'b00010_0000_0000_00;end//8011
??????????? 274: begin CS=2'b10;LEDCS=15'b00100_0000_0000_00;end//8012
??????????? 275: begin CS=2'b10;LEDCS=15'b01000_0000_0000_00;end//8013
??????????????? 276: begin CS=2'b10;LEDCS=15'b10000_0000_0000_00;end//8014
??????????????? endcase
????????????? end
??
??? end
??
?
always @(negedge wr_en or posedge CLR or posedge OC ) //WR下降延寫數(shù)據(jù)
??? begin
??????? if(OC)
????? begin?????????????????????????????
? DataBF=0;
? OUT30[59:0]=60'hfffffffffffffff;
????? end
??????? else if(CLR)???????
????? begin
??????????????
? DataBF=0;
? OUT30[59:0]=60'hfffffffffffffff;
????? end?????????
? else
????? begin?????????????????????
??????? if(Data[0])
??? DataBF[1:0]=2'b10;
? else
??? DataBF[1:0]=2'b01;???????????????????????????
??????????? if(Data[1])
????????????????????? DataBF[3:2]=2'b10;
? else
??? DataBF[3:2]=2'b01;?????????????
??????????? if(Data[2])
????????????????????? DataBF[5:4]=2'b10;
? else
??? DataBF[5:4]=2'b01;?????????????????
??????????? if(Data[3])
????????????????????? DataBF[7:6]=2'b10;
? else
??? DataBF[7:6]=2'b01;
??????? if(Data[4])
????????????????????? DataBF[9:8]=2'b10;
? else
??? DataBF[9:8]=2'b01;
??????? if(Data[5])
????????????????????? DataBF[11:10]=2'b10;
? else
??? DataBF[11:10]=2'b01;
??????? if(Data[6])
????????????????????? DataBF[13:12]=2'b10;
? else
??? DataBF[13:12]=2'b01;
??????? if(Data[7])
????????????????????? DataBF[15:14]=2'b10;
? else
??? DataBF[15:14]=2'b01;
????????
??????????????? case(IOADD)
??????????? 257: begin OUT30[15:0] =DataBF;end//8001
??????????????? 258: begin OUT30[31:16]=DataBF;end//8002???????????
??????????????? 259: begin OUT30[47:32]=DataBF;end//8003
??????????? 260: begin OUT30[59:48]=DataBF;end//8004
??????????????? endcase
??????????????? case(IOADD)
??????????????? 278: begin OUT30[1:0]=2'b10;end//8016
??????????????? 279: begin OUT30[1:0]=2'b01;end//8017
??????????????? 280: begin OUT30[3:2]=2'b10;end//8018
??????????????? 281: begin OUT30[3:2]=2'b01;end//8019
??????????????? 282: begin OUT30[5:4]=2'b10;end//801A
??????????????? 283: begin OUT30[5:4]=2'b01;end//801B
??????????????? 284: begin OUT30[7:6]=2'b10;end//801C
??????????????? 285: begin OUT30[7:6]=2'b01;end//801D
??????????????? 286: begin OUT30[9:8]=2'b10;end//801E
??????????????? 287: begin OUT30[9:8]=2'b01;end//802F
??????????????? endcase
??????????????? case(IOADD)
??????????????? 288: begin OUT30[11:10]=2'b10;end//8020
??????????????? 289: begin OUT30[11:10]=2'b01;end//8021
??????????????? 290: begin OUT30[13:12]=2'b10;end//8022
??????????????? 291: begin OUT30[13:12]=2'b01;end//8023
??????????????? 292: begin OUT30[15:14]=2'b10;end//8024
??????????????? 293: begin OUT30[15:14]=2'b01;end//8025
??????????????? 294: begin OUT30[17:16]=2'b10;end//8026
??????????????? 295: begin OUT30[17:16]=2'b01;end//8027
??????????????? 296: begin OUT30[19:18]=2'b10;end//8028
??????????????? 297: begin OUT30[19:18]=2'b01;end//8029
????????????????? endcase
????????????????? case(IOADD)
??????????????? 298: begin OUT30[21:20]=2'b10;end//802A
??????????????? 299: begin OUT30[21:20]=2'b01;end//802B
??????????????? 300: begin OUT30[23:22]=2'b10;end//802C
??????????????? 301: begin OUT30[23:22]=2'b01;end//802D
??????????????? 302: begin OUT30[25:24]=2'b10;end//802E
??????????????? 303: begin OUT30[25:24]=2'b01;end//802F
??????????????? 304: begin OUT30[27:26]=2'b10;end//8030
??????????????? 305: begin OUT30[27:26]=2'b01;end//8031
??????????????? 306: begin OUT30[29:28]=2'b10;end//8032
??????????????? 307: begin OUT30[29:28]=2'b01;end//8033
????????????????? endcase
????????????????? case(IOADD)
??????????????? 308: begin OUT30[31:30]=2'b10;end//8034
??????????????? 309: begin OUT30[31:30]=2'b01;end//8035
??????????????? 310: begin OUT30[33:32]=2'b10;end//8036
??????????????? 311: begin OUT30[33:32]=2'b01;end//8037
??????????????? 312: begin OUT30[35:34]=2'b10;end//8038
??????????????? 313: begin OUT30[35:34]=2'b01;end//8039
??????????????? 314: begin OUT30[37:36]=2'b10;end//803A
??????????????? 315: begin OUT30[37:36]=2'b01;end//803B
??????????????? 316: begin OUT30[39:38]=2'b10;end//803C
??????????????? 317: begin OUT30[39:38]=2'b01;end//803D
????????????????? endcase
????????????????? case(IOADD)
??????????????? 318: begin OUT30[41:40]=2'b10;end//803E
??????????????? 319: begin OUT30[41:40]=2'b01;end//803F
??????????????? 320: begin OUT30[43:42]=2'b10;end//8040
??????????????? 321: begin OUT30[43:42]=2'b01;end//8041
??????????????? 322: begin OUT30[45:44]=2'b10;end//8042
??????????????? 323: begin OUT30[45:44]=2'b01;end//8043
??????????????? 324: begin OUT30[47:46]=2'b10;end//8044
??????????????? 325: begin OUT30[47:46]=2'b01;end//8045
??????????????? 326: begin OUT30[49:48]=2'b10;end//8046
??????????????? 327: begin OUT30[49:48]=2'b01;end//8047
????????????????? endcase
????????????????? case(IOADD)
??????????????? 328: begin OUT30[51:50]=2'b10;end//8048
??????????????? 329: begin OUT30[51:50]=2'b01;end//8049
??????????????? 330: begin OUT30[53:52]=2'b10;end//804A
??????????????? 331: begin OUT30[53:52]=2'b01;end//804B
??????????????? 332: begin OUT30[55:54]=2'b10;end//804C
??????????????? 333: begin OUT30[55:54]=2'b01;end//804D
??????????????? 334: begin OUT30[57:56]=2'b10;end//804E
??????????????? 335: begin OUT30[57:56]=2'b01;end//804F
??????????????? 336: begin OUT30[59:58]=2'b10;end//8050
??????????????? 337: begin OUT30[59:58]=2'b01;end//8051
??????????????? endcase
??????????????? end
????????
? end?
endmodule
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