ARM? Cortex?-M3 core

The Cortex?-M3 processor is the latest generation of ARM? processors for embedded

systems. It has been developed to provide a low-cost platform that meets the needs of MCU

implementation, with a reduced pin count and low-power consumption, while delivering

outstanding computational performance and an advanced system response to interrupts.

n 32-bit ARM? Cortex?-M3 processor core

n Up to 72 MHz operation frequency

n Single-cycle multiplication and hardware divider

n Integrated Nested Vectored Interrupt Controller (NVIC)

n 24-bit SysTick timer

The Cortex?-M3 processor is based on the ARMv7 architecture and supports both Thumb

and Thumb-2 instruction sets. Some system peripherals listed below are also provided by

Cortex?-M3:

n Internal Bus Matrix connected with ICode bus, DCode bus, system bus, Private

Peripheral Bus (PPB) and debug accesses (AHB-AP)

n Nested Vectored Interrupt Controller (NVIC)

n Flash Patch and Breakpoint (FPB)

n Data Watchpoint and Trace (DWT)

n Instrument Trace Macrocell (ITM)

n Memory Protection Unit (MPU)

n Serial Wire JTAG Debug Port (SWJ-DP)

n Trace Port Interface Unit (TPIU)

On-chip memory

n Up to 1024 Kbytes of Flash memory

n Up to 32 Kbytes of SRAM

The ARM? Cortex?-M3 processor is structured in Harvard architecture which can use

separate buses to fetch instructions and load/store data. 1024 Kbytes of inner Flash and 32

Kbytes of inner SRAM at most is available for storing programs and data, both accessed

(R/W) at CPU clock speed with zero wait states. The Figure 6. X32F1003xx memory map

shows the memory map of the X32F1003xx series of devices, including code, SRAM,

peripheral, and other pre-defined regions.